eLRM Foreign Access and Interfaces TF - Verilog code

[<pitchumani.guru@wipro.com>]

Hi,

With reference to section 25.1.1 of the LRM, is the syntax example for
the 'verilog code' construct fine? Will it require a more generic
example (specifying the begin/end statements)?


Syntax example as in page 795

Verilog code {"initial clk = 1'b1;};
Unit router {
	Verilog code {"initial "; s};
	Verilog code ls;
};


regards
pitchu



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