RE: eLRM Foreign Access and Interfaces TF - VHDL code

["Hamilton Carter" <hcarter@verisity.com>]

Hi,

I propose that the original paragraph:

A full or a relative VHDL path to the signal. If the signal has more than
one driver, one driver in the DUT and one in the e program, for exam-
ple, then the signal must be of a resolved type. If this name is not a con-
stant, it is calculated after the final step of pre-run generation.

Should read:

A full or a relative VHDL path to the signal.  If this name is not a con-
stant, it is calculated after the final step of pre-run generation.  If the
signal has more than one driver, one driver in the DUT and one in the e
program, for example, then the signal must be of a resolved type.

Best Regards,
Hamilton Carter


-----Original Message-----
From: owner-1647-l@verificationvault.com
[mailto:owner-1647-l@verificationvault.com]On Behalf Of
pitchumani.guru@wipro.com
Sent: Tuesday, February 03, 2004 10:59 AM
To: 1647-fitf@ieee1647.org
Subject: eLRM Foreign Access and Interfaces TF - VHDL code



Hello all,


In section 25.2.2 (VHDL Driver)  the crossed lines of the paragraphs
need to be taken care (page 816).


Is this to be omitted or modified? Can we raise an issue on the same?

Regards
pitchu

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