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Re: Ports

Pitchu,

These are modeling aspects of two languages. I think they are not
relevant for our working group, at least in its current scope
definition.

Regards,
Vitaly

pitchumani.guru@wipro.com writes:
 > 
 > Hi,
 > 
 > 
 > 
 > The following were some of the considerations for SystemC interface to
 > SystemVerilog (as per Rob Slater) 
 > 
 > 
 > 
 > o Scheduling semantics between the two simulators (including triggering
 > events)
 > 
 > o Binding signals  between SystemC models and SystemVerilog ones
 > 
 > o Calling SystemC methods from SystemVerilog
 > 
 > o Calling SystemVerilog tasks and functions from SystemC
 > 
 > 
 > 
 > Do we need to look along these lines for our taskforce? Will ports be
 > able to handle these aspects?
 > 
 > 
 > 
 > Rgds
 > 
 > pitchu
 > 
 > 
 > 
 > 
 > 
 > 
 > 
 > 
 > Confidentiality Notice
 > 
 > The information contained in this electronic message and any attachments to this message are intended
 > for the exclusive use of the addressee(s) and may contain confidential or privileged information. If
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 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>Hi,</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>&nbsp;</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>The following were some of the
 > considerations for SystemC interface to SystemVerilog (as per Rob Slater)&nbsp;
 > </span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>&nbsp;</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>o Scheduling semantics between the two
 > simulators (including triggering events)</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>o Binding signals&nbsp; between SystemC
 > models and SystemVerilog ones</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>o Calling SystemC methods from SystemVerilog</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>o Calling SystemVerilog tasks and
 > functions from SystemC</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>&nbsp;</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>Do we need to look along these lines for
 > our taskforce? Will ports be able to handle these aspects?</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>&nbsp;</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>Rgds</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 color=navy face=Arial><span style='font-size:
 > 10.0pt;font-family:Arial;color:navy'>pitchu</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
 > font-family:Arial'>&nbsp;</span></font></p>
 > 
 > <p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
 > font-family:Arial'>&nbsp;</span></font></p>
 > 
 > </div>
 > 
 > </body>
 > 
 > </html>
 > 
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