IEEE 1647 temporal expressions task force

[David Van Campenhout <dvc@verisity.com>]

All,

I would like to nominate myself to head the temporal expressions task
force (TE_TF). A few words about myself:

I have been with Verisity Design as an R&D engineer since 1999. I have
worked in the areas of test generation, temporal logics, and e
synthesis. I earned a PhD in Electrical Engineering from the
University of Michigan.

I have served on Accellera's Formal Verification Committee (FVTC)
since the beginning of 2001. This is the committee that has drafted
the PSL standard. I actively participated in several subcommittees. I
am proud of the work of the FVTC, and in particular of that of the LRM
subcommittee, and I would like to strive for the same high quality and
constructivism in the IEEE 1647 temporals task force.

I invite anybody interested to join this task force and work towards
making IEEE 1647 a standard.

Best regards,

David
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David Van Campenhout [mailto:dvc.verisity.com]           Verisity Design
Tel.: +1 650 934-6878                               Fax: +1 650 934-6801