RE: Task forces so far

["Pitchumani Guruswamy" <pitchumani.guru@wipro.com>]

Hi,

I would like to work on the "Foreign (HDL) access and interfaces
(FI_TF)"
I've worked on the tools, interfaces of major EDA vendors.

Some thoughts:
1) Since verification essentially involves running jobs on server farms
, does the language need to support/interface with the existing tools ?
2) How does the language revisions to Verilog/VHDL impact?



Regards
pitchu

-----Original Message-----
From: owner-1647-l@verificationvault.com
[mailto:owner-1647-l@verificationvault.com] On Behalf Of Yaron Kashai
Sent: Monday, November 03, 2003 11:20 PM
To: 1647-l@ieee1647.org
Subject: Task forces so far


Hello again,

Here is a summary of the sign-up to various TFs so far. I've considered
the first person to sign up to be the lead.

Please let me know if I missed anything, and kindly consider joining to
your favorite TF. It would be great if we could get number 7, 8 started
soon. All TFs need more members.

As a general guideline, TFs should have 3 to 5 members. Also, please
keep in mind that these memberships need to be approved by the WG -
hopefully in the December 8 meeting.

Cheers,

-- yaron


2. Basic language task force (BL_TF)
    - Chris Macionski
    - Silas McDermott

3. AOP task force (AOP_TF)

4. Constraints and generation (TG_TF)
    - Ken Sailor

5. Coverage task force (COV_TF)
    - Andy Piziali
    - Darren Galpin

6. Temporal expressions (TE_TF)
    - David Van Campenhout
    - Achutha Jois

7. TCMs and concurrent semantics (TCM_TF)
8. Foreign (HDL) access and interfaces (FI_TF)
9. e libraries (LIB_TF)
10. e reflection API (RF_TF)
11. e synthesis task force (SYN_TF)

  
              


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