David Van Campenhout introducing himself

[David Van Campenhout <dvc@verisity.com>]

Per Yaron Kashai's request that the task force leads introduce themselves, 
I am David Van Campenhout (the "Van" is part my last name) and I
would like to lead the temporal expression task force (TE_TF). I have
been with Verisity Design as an R&D engineer since 1999. I have worked
in the areas of test generation, temporal logics, and e synthesis. I
earned a PhD in Electrical Engineering from the University of
Michigan. I have served on Accellera's Formal Verification Committee
(FVTC), working on the PSL standard, since the beginning of 2001. I
actively participated in several subcommittees.

David
------------------------------------------------------------------------
David Van Campenhout [mailto:dvc.verisity.com]           Verisity Design
Tel.: +1 650 934-6878                               Fax: +1 650 934-6801