KEYWORDS
========

1) predefined (pseudo) routines
all_values
get_all_units
error
error_f
message
message_f
---

2) predefined (pseudo) routines
dut_error
dut_error_f
---

3) predefined (pseudo) methods
get_enclosing_unit
try_enclosing_unit
---

4) automatic variables
index
me
result
it
---

5) time units
hr
min
sec
ms
us
ns
ps
fs
---

6) for each using index (my_index) prev (my_prev)
prev
---

7) list (key:id) of s
list
key
of
---

8) m() is {
is
---

9) for each (s) in lof_s
in
---

TRUE
FALSE
NULL
UNDEF
MAX_INT
MIN_INT
MAX_UINT


package
private
protected


bool
char
int
uint
bit
nibble
byte
time

bits
bytes


type
struct
unit
extend
like
routine
sequence


attribute

when

bind
undefined
external
empty
inout
out

keep
gen
soft
select
before

event
on
expect
assume

cover
using
item
transition
cross
ranges
range


keeping
var
break
continue
if
then
else
case
default
repeat
until
while
for
from
matching
to
do
step
try
compute
return
start
wait
sync
now
emit
consume
new
with
check
assert
that

print

force
release


exec
eventually
cycle
detach
true
rise
fall
change
delay
fail


as_a
not
or
and
nor
nand
nxor



KEYPHRASES
==========

is empty
is undefined
using index
list of
in sequence
in unit
is not empty
in range
not in

c export

verilog time
vhdl time

method type

is c routine
dynamic c routine
foreign dynamic c routine

is inline
is inline only
is also
is first
is only

keep gen_before_subtypes
keep reset_gen_before_subtypes

is instance

cvl method
cvl call
cvl callback

cvl call async
cvl method async
cvl callback async

verilog simulator
vhdl simulator
verilog task
verilog function
verilog variable
verilog code
vhdl code
vhdl procedure
vhdl function
vhdl driver
vhdl object

for each
in reverse
for each file
for each line
in file
down to

all of
first of
state machine

simple port of
buffer port of
event port
call port of
method port of

using also

is a
is not a

RESERVED NAMES
==============

RESERVED PHRASES
================

ISSUES
======