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Officers
Officers of the eWG
Yaron Kashai - Chair (elected
6/14/03)
"I
started my career at National Semiconductor in 1985, working on
distributed computing, and later managing the validation and test
automation team focused on the verification of high end CPUs, PC
peripherals and wireless
applications.
I've joined Verisity in 1996, serving
in a number of field and R&D positions, with responsibilities
including the setup of US field operations, development of the e
temporal language and test bench synthesis. I currently serve
as VP research for Verisity."
Steve Pearlmutter - Vice
Chair (elected 10/27/03)
"My
experience in design verification dates back to 1991. During that
time, I've been both a developer of tools and an end user, including
experience with Vera, System C, and custom in-house tool development.
From 1997 to 2000, I was a Verisity
Consulting Engineer, working with customers to teach them Specman and e
and to integrate Specman into their verification flow. My
responsibilities there also included working closely with R&D on
new features, new releases, and resolving customer issues. Since
2000, I've been using Specman on a number of projects as either a
consultant or verification engineer.
At present, I am an independent
verification consultant, largely focused on Specman-based verification."
Serrie-justine Chapman -
Secretary (elected 2/09/04)
"I am Serrie-justine Chapman and I am putting myself forward as
secretary. I
have a first in Computing for real time systems (mixed
hardware/software
engineering course) and have been working for the past two years with
Infineon Technologies as a verification engineer. I am familiar with
random, directed and formal testing methodologies. I have been using
Specman
for roughly 3 1/2 years primarily with eVC's and also with an e based
ISG."
Task force leads
Chris Macionski
"I'm
currently with Bright Eyes Consulting, specializing in
verification and verification methodology. I am familiar with
VHDL, Verilog, Specman, Vera, and SystemC. I've used
Specman for about 4 years, both as a verification consultant and
as a trainer. I've worked with companies both in N America
and Europe. Prior to going to BEC, I was a consultant with
both Qualis Design and Cadence Design."
Matan Vax
"I
got to lead the AOP task force (which might be united with Reflection
TF in the next week’s meeting). I’ve been working for Verisity in the
last almost 4 years as a software engineer in the lang uage group, and
before that I was in the CAD group in Intel Haifa. I have an interest
in OO lang uages and in new modeling paradigms such as AOP. I was
involved in the definition of Reflection API for ‘e’, and ‘e’ support
for encapsulation. "
Vitaly
Lagoon (elected 4/4/05)
"Dr.
Lagoon received his B.Sc. and M.Sc in Mathematics and Computer Science
from Ben-Guring University, Israel,
and his Ph.D. in Computer Science from the University of Melbourne, Australia.
He is a consultant working with the Constraints and Generation team of
Verisity. In this role he is actively involved in design and
development of constraint solving technologies used in the company
products.
Dr. Lagoon also works as a part-time researcher at the CSSE Dept. of Melbourne University.
His main research interests include constraint solving and modeling,
program analysis and constraint logic programming. He is one of the
contributors of the constraint programming research project of NICTA Victoria Laboratory.
The list of publications (accurate, more or less) is available from DBLP
Bibliography Database."
Andy Piziali
"I am
Andrew Piziali, product engineer with Verisity since the fall of
1999. I have been in the field of design verification since1983,
almost exclusively verifying processors (mainframes, supercomputers and
microprocessors). Since 1991, I have been strongly focused on
functional coverage measurement and analysis. I currently lead
the coverage task force."
David Van Campenhout
"I
have been with Verisity Design as an R&D engineer since 1999. I
have worked in the areas of test generation, temporal logics, and e
synthesis. I earned a PhD in Electrical Engineering from the University
of Michigan.
I have served on Accellera's Formal
Verification Committee (FVTC) since the beginning of 2001. This is the
committee that has drafted the PSL standard. I actively participated in
several subcommittees. I am proud of the work of the FVTC, and in
particular of that of the LRM subcommittee, and I would like to strive
for the same high quality and constructivism in the IEEE 1647 temporals
task force."
Matthew Morley
"i
have been with Verisity since 1998 and have worked on the semantics of
temporal "e", and the concurrent language fragment; i currently lead
the synthesis team. before coming to Verisity i worked at Leeds
University in the UK with Prof. Graham Birtwistle looking at formal
models for asynchronous hardware; before that i worked with Prof. Axel
Poigne in Bonn looking at Esterel and other fun synchronous programming
languages, and developed a (rather good at the time!) compiler for pure
Esterel. i obtained my PhD (emphasis on theory of
concurrency, programming language
semantics, and applied formal methods) from the University of Edinburgh
(1996). "
Pitchumani Guruswamy
"I
work with Wipro technologies on EDA/Design infrastructure. I have
worked with Verilog/VHDL/Specman e for about 5 years and on EDA
tools/methodologies for about 10 years from various vendors. "
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